Optimization of Floating-Point based Finite Difference Methods on FPGAs

Finite Difference (FD) methods are the most prevalent numerical modelling algorithms for evaluating initial or boundary value problems in scientific and engineering applications. Unfortunately, simulating time evolutions for transient physical phenomenon is computationally demanding and data-intensive. In this paper, we introduce an efficient implementation of FD computing engine on FPGA-based Reconfigurable Computing (RC) platform. Instead of following the formal high-order FD expressions with standard IEEE-754 compliant floatingpoint arithmetic units, we propose a new class of optimized finite-accurate FD schemes, whose FD coefficients are optimized to be represented with only a few binary bits without deteriorating numerical accuracy criterions. Furthermore, in order to simplify the implementation of subsequent floating-point summations, we replace the conventional costly floating-point adder tree by a floating-point/fixed-point hybrid accumulator based on group-alignment technology. The resulting fullypipelined FD computing engine with finite accurate coefficients can provide us similar or even better worst case relative and absolute rounding errors than standard floating-point arithmetic, but consumes only a fraction of hardware resources. Moreover, the regular layout and localized interconnections of our design lead to higher data throughput and much less pipeline stages especially for FD schemes with wide stencils.